IBM has unveiled a new chip design that it says could enable manufacturers to fit 100 billion transistors on a silicon chip the size of a fingernail, using a stacking approach the company compares to building a skyscraper rather than spreading components across a flat surface. The technology, called NanoStack, represents the equivalent of a 0.7 nanometre process node—believed to be the first known chip technology below 1nm. In tests, IBM said its prototype performed 50% better than its own 2nm chip and was 70% more energy efficient. However, the company cautioned that it will be several years before the technology is ready for production.

The announcement marks a significant step in the semiconductor industry’s shift toward three-dimensional chip designs, as manufacturers confront the physical limits of making transistors ever smaller on flat silicon surfaces.

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What IBM Has Built

Jay Gambetta, director of IBM Research and IBM Fellow, described NanoStack as a “landmark moment” for the future of chips. “With our new NanoStack architecture, we’re not just making smaller transistors, we’re reinventing how chips are built to deliver dramatically more power and energy efficiency,” he said.

The approach layers sheets of transistors on top of each other, creating a vertical stack rather than the traditional horizontal layout. Transistors are the building blocks of silicon chips, providing computing power for everything from smartphones and laptops to the powerful computers housed in data centres that process streaming, online banking, and generative AI workloads.

For decades, the number of transistors that can be placed on a chip has doubled roughly every two years—a phenomenon known as Moore’s Law. But with billions of transistors now on some chips, sustaining that pace has grown more difficult, and experts broadly agree it cannot continue indefinitely using traditional methods. The industry has increasingly turned to 3D alternatives that alter the shape and arrangement of transistors rather than simply shrinking them.

According to IBM Research’s official announcement and technical briefing on NanoStack architecture, the prototype achieved its performance gains by stacking transistor layers vertically, a departure from the flat-plane approach that has dominated semiconductor manufacturing for six decades.

Professor Alan Woodward, a computer scientist at Surrey University, compared the technology to urban planning. “IBM’s NanoStack is like proposing a 100-storey skyscraper,” he said, adding that in his view, the firm’s closest rivals, such as Samsung and Intel, are closer to 30-50 storey buildings with their own 3D chip work. “I think it’s fair to say IBM’s proposals are the most ambitious.”

As our coverage of the global semiconductor industry and the race to extend Moore’s Law documented, chip designers have been exploring 3D architectures for years as the physical limits of miniaturisation approach. At 2nm, the current industry-standard size, gate lengths are measured in single-digit numbers of atoms.

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The Engineering Challenges

Building upward creates new problems. The most significant is heat: transistors generate warmth as they work, and heat rises through the layers. When the layers between transistors are too thin, they can prevent the transistors from switching off when required, causing the chip to malfunction.

Professor Woodward noted that while IBM’s proposal is the most ambitious, all 3D chip designers face the same thermal management challenges. IBM has not claimed to have solved the heat problem entirely, but has demonstrated a working prototype that manages it sufficiently to deliver the performance and efficiency gains the company reported.

The 70% energy efficiency improvement is particularly significant for the data centre industry, which is spending hundreds of billions of dollars this year on AI infrastructure. Google, Amazon, and Meta collectively plan to invest roughly $650 billion in AI in 2026, according to company disclosures. Chips that deliver more performance for less electricity could reshape the economics of that investment.

According to semiconductor industry analysis of 3D chip development programmes at Samsung, Intel, and TSMC, all three major manufacturers are pursuing versions of vertical transistor stacking, though none have yet demonstrated a working prototype at the equivalent of 0.7nm.

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What This Means for Moore’s Law

Moore’s Law—the observation that transistor counts double roughly every two years—has been declared dying or dead many times over the past decade. IBM’s breakthrough does not revive it in its original form. Instead, it demonstrates a different path to increasing transistor density: not by making individual components smaller, but by arranging them in three dimensions.

The distinction matters. For consumers, a chip with 100 billion transistors delivers more computing power regardless of how those transistors are arranged. For the industry, the shift from flat to vertical represents a fundamental change in manufacturing approach. The companies that master vertical stacking will control the next generation of chip performance.

IBM does not manufacture chips at scale. It designs them and licenses the technology to manufacturers. The NanoStack announcement is a signal that the design pathway below 1nm is viable. Who manufactures those designs, and where, will shape the semiconductor industry’s competitive landscape for years to come.

As our analysis of the semiconductor manufacturing landscape and foundry competition explored, TSMC in Taiwan, Samsung in South Korea, and Intel in the United States are all investing heavily in next-generation chip production. IBM’s licensing model means its designs could eventually be manufactured by multiple partners.

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FAQ

What is IBM’s NanoStack?

NanoStack is a new chip design that stacks layers of transistors vertically rather than arranging them on a flat surface. IBM says it can fit 100 billion transistors on a fingernail-sized chip and perform at the equivalent of a 0.7nm process node.

How small is 0.7 nanometres?

A nanometre is a billionth of a metre—roughly the size of a few atoms. The current industry-standard size is around 2nm. IBM’s 0.7nm equivalent would be the first known chip technology below 1nm.

When will these chips be available?

IBM says it will be several years before the technology is ready to go into production. The current prototype is a laboratory demonstration, not a commercial product.

Why build chips upward instead of making transistors smaller?

The physical limits of miniaturisation are approaching. At 2nm, gate lengths are already measured in single-digit numbers of atoms. Stacking transistors vertically allows manufacturers to increase density without further shrinking individual components.

What are the main challenges with 3D chip designs?

Heat is the biggest problem. Transistors generate warmth as they work, and heat rises through the layers. When layers are too thin, transistors can fail to switch off, causing the chip to stop working.